Area efficient and speed performance of pre encoded multiplier by using non redundant radix-4 signed digit encoding

The paper introduces an architecture for 32-bit pre-encoded multipliers for Digital Signal Processing applications based on the off-line encoding of coefficients. In this we uses the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses two different the digit values {-1, 0, +1, +2} or {-2, -1, 0, +1}, is proposed for efficient multiplier design with less complex computation implementation. The proposed architecture is implemented on Xilinx 13.1 ISE design Suite on the target device as xc6slx16-3csg324 and simulation are carried out on ISIM simulation tool. The implemented design is area and speed efficient as compared to conventional pre-encoding modified booth multiplier.