A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies

This paper proposes an ESD technology strategy for characterization, evaluation and benchmarking the ESD "robustness" of CMOS semiconductor technologies. The ESD methodology uses a set of CMOS "building block" ESD test structures, matrices of critical ESD layout variables, electrical characterization parameters, and testing and extraction procedures, and ESD metrics. This work is the first step in the development of a common ESD language.