The scaling issues of subnanometer EOT gate dielectrics for the ultimate nano CMOS technology

An overview of the state-of-the art of the ongoing research on high-k gate dielectrics for the advanced nano-CMOS technology is presented. The most promising high-k candidates for next-generation MOS devices are highlighted. The associated performance degradation and the scaling limitations of these high-k materials are also discussed and emerging solutions and optimization schemes for the subnanometer equivalent oxide thickness (EOT) technology are proposed.