An overview of the modeling and simulation of the single event transients at the circuit level

The single event transients (SETs) are a common source of malfunction in nano-scale CMOS integrated circuits. For this reason, evaluation of the SET effects and application of appropriate measures for their mitigation are fundamental tasks in the design of advanced radiation hardened integrated circuits. In general, SET analysis is based on the multi-scale modeling and simulation approach comprising four main phases: modeling and simulation of radiation-matter interactions, device-level modeling and simulation, circuit-level modeling and simulation and logic-level modeling and simulation. In order to reduce the time and cost of the evaluation and design processes, a lot of effort is invested into the development of appropriate models which could provide accurate SET simulations at the circuit level. The circuit-level simulations provide a good trade-off between the complexity and speed of simulations, and at the same time ensure very good accuracy. This paper reviews the approaches for modeling and simulation of SET effects at the circuit level, emphasizing the major advantages and disadvantages of each approach.