A 300 MHz burst-pipelined CMOS SRAM macro with folded bit-line scheme

This paper describes a new architecture and schemes for high speed SRAM. It is summarized as follows: (1) a folded bit-line architecture (FBLA) to reduce the delay time of bit-line by decreasing the parasitic capacitance, to reduce the area; (2) a double word-line activation (DWLA) technique to increase the data-rate twice and minimize row path delay, and (3) a high speed sensing scheme to decrease the delay time of sense amplifier. To verify these, a 8 Kb SRAM was designed using 0.6 /spl mu/m technology; it realized a 600 Mbyte/s (300 M/spl times/8/spl times/2) data-rate and the die size is 2.8 mm/spl times/0. 85 mm.