A minimal hardware constrained scheduling algorithm for VLSI design automation

In this paper, we present a new VHDL intermediate format CDDG (control dominated data graph) and a minimal hardware constrained scheduling algorithm for VLSI design automation. The intermediate format, CDDG, represents the constraints which limit hardware design such as conditional branch, sequential operation and time constraints. The proposed scheduling algorithm could handle the conditional branches effectively and could check the timing constraints efficiently. It minimizes the total operating time by reducing the number of the constraints to be as maximal as possible, searching a few paths produced by conditional branches. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.