A study on logic design and architecture simulator design of a new on-chip multiprocessor

We propose a novel on-chip multiprocessor architecture and a program-driven simulator for the processor. Today's superscalar processors already have very complicated control logics to resolve dependencies while increasing the instructions per-cycle (IPC). With the advent of semiconductor technology, integrating multiple processors into a chip is a promising alternative for increasing IPC. The new architecture simulator provides a coarse grain multithreaded architecture simulation environment. It runs various multithreaded benchmark programs. We can find out how various architecture-dependent parameters affect the behavior and performance of the on-chip multiprocessor as it includes not only the instruction set architecture but also the microarchitecture.