Compensation of two-stage operational amplifiers for switched-capacitor applications

Due to the decrease of power supply voltage in future CMOS technologies, two-stage amplifiers become an interesting alternative to cascoded single-stage architectures in switched-capacitor applications. The main handicap of two-stage amplifiers is their limited speed ability, which is critically dependent upon the compensation method used. Thus, we compare in this paper different compensation techniques. Techniques that allow one to cancel a pole by a zero seem particularly interesting. Therefore matching requirements for pole zero cancellation are investigated and the possibility of meeting them in switched-capacitor circuits is discussed.