New MRC Adder-Based Reverse Converter for the Moduli Set {2n, 22n+1 − 1, 22n+2 − 1}

In this paper, we propose a reverse converter for a length 3 larger 5n bit dynamic range (DR) moduli set {2ⁿ, 2²ⁿ⁺¹ − 1, 2²ⁿ⁺² − 1}. The reverse converter is based on the mixed radix conversion (MRC) algorithm. In addition, we further simplified the resulting architecture to obtain a reverse converter that utilizes only 1 level of Carry Save Adder together with three Carry Propagate Adders. The proposed converter is purely adder based. Theoretically speaking, our proposal has a delay of (9n+7)tFA with an area cost of (9n+5)FAs and (2n+2) HAs, where FA, HA and tFA represent Full Adder, Half Adder and delay of a Full Adder, respectively. Consequently, we compared the proposed scheme with the state of the art and other existing (5n) bit DR moduli sets with their associated reverse converters both theoretically and experimentally. The theoretical analysis indicates that, for the same moduli set, the best converter requires (22n + 12) HAs and exhibits a delay of (14n + 8)tFA. Additionally, we described the proposed converter and the state-of-the-art converter in VHDL, and then implemented them using FPGA technology. From the results, our proposal outperforms the state of the art with ∼ 35.98 and 6.76% in terms of hardware resources and conversion time, respectively.