A 10-bit high-speed low-power CMOS D/A converter in 0.2 mm/sup 2/

This paper describes design and implementation of a 10-bit current steering CMOS D/A converter for a direct digital synthesizer. A very small circuit area is achieved by constructing the binary weighted currents using two sized unit current sources. This structure also leads to low power consumption since no decoding logic is needed. The glitch energy is reduced by using properly overlapped and amplitude limited steering signals for the differential current switches. The measured DNL is 0.43 LSB and INL 0.35 LSB. According to simulations the circuit achieves >60 dBc SFDR at 250 MS/s sampling rate with power dissipation of 17 mW@3.3 V. The circuit is implemented in 0.5 /spl mu/m CMOS technology.