Design of Reconfigurable VLSI Architecture for Hybrid Arithmetic in $GF(2^m)$

In this paper, a redundant canonical basis representation with the irreducible all one polynomial (AOP) is defined. Three novel designs of a multiplier in a redundant canonical basis over $GF(2^m)$ are presented, based on which a new reconfigurable VLSI architecture of hybrid finite-field arithmetic in $GF(2^m)$ is proposed that is able to perform multiplication, squaring and inversion in both redundant canonical basis and normal basis. The unique properties of this reconfigurable VLSI architecture are that it can be reconfigured on-line and its ratio of throughput/area is much higher than the traditional FPGA approach. The proposed architectures are highly modular and well suited for high-speed VLSI implementations. The results of the simulations indicate that the proposed architectures offer higher speed, lower hardware complexity and more flexible parallel/serial structures than the previous relevant works.