Upset hardened latch as data synchronizer

Upset hardened dual-interlocked cell (DICE) [1] has found an important place in circuits for space applications due to its ability to mitigate single event upsets (SEUs). In this paper, we show that DICE latch/flip-flop exhibits better immunity to metastability compared to D flip-flop, and can be used as data synchronizer. Metastablity constant (τ), whose inverse captures the ability of the latch to exit from metastable state is about one-half in DICE compared to a similar sized standard latch. This would mean an improvement of 7x in mean-time between failure (MTBF) due to metastability. We have simulated both DICE and D flip-flops designed in different technology nodes-180nm, 130nm, 65nm, and 40nm for planar devices and 20nm, 16nm, 14nm, 10nm and 7nm for FinFET devices along with process variations. We have done pre and post-layout simulations of DICE and D flip-flops taking into account process corners variations. We report that DICE exhibits better metastability hardness compared to D flip-flop across all technology nodes, except at 7nm. We also report that in all the cases τ of DICE flip-flop is lower than that of D flip-flop.