Design of a high flexible block-based computational CMOS image sensor

This paper proposed the architecture of a linear current-mode CMOS image sensor integrated parallel processing unit enabling various block-level calculation during the read-out procedure. Combinational logic with two scanning DFF chains and global control signals as input generates the output to address the right pixels with high flexibility. Four current conveyors are used to perform CDS function for the chosen pixels. Four digitally programmable scaling units and a TIA based arithmetic unit are integrated for the proposed computation procedure. The 240×200 image sensor was fabricated in 0.18um standard 4T CIS technology with a pixel size of 9um×9um and a fill factor of 30%. One computation operation can be done within 3us with a power consumption of 309uW in average for analog circuits.