Routability-driven macro placement considering pins location

Development of semiconductor process makes devices have smaller area, lower power, and reduced wire connections. To achieve this purpose, macro placement plays an important role in the design flow. In this paper, we present a routability-driven macro placement algorithm considering pins location to optimized scaled routing congestion and macro placement area. By considering pins location, reclassify all macros and program floating border value, we improves routing congestion and placement area flexibly. Experimental results show that we can improve the performance effectively by integrating our macro placer with other standard-cell placers, such as NTUplace3, to minimize routing congestion with only a little area overhead.