Comparison of sequence diagram from execution against design-time state specification

Simulating real world applications containing many functionalities using programs tend to become very complex in structure and behaviour. Validating such programs for its correctness require correct outputs and their ability to cope with erroneous scenarios. This work proposes a methodology for the verification of such programs defined using Java, based on their design-time and run-time model, where both the models are defined using the behavioural Unified Modeling Language state and sequence diagrams. The design-time behaviour is depicted by the state diagram and the run-time behaviour by sequence diagram, which is defined over the execution trace of the program. This work includes an automated and algorithmic approach to perform validation of application software.