Design-for-testability in reversible logic circuits based on bit-swapping

The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low-power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ⩾ 1. While analyzing testability issues in a reversible circuit, the missing-gate fault model is often used for modeling physical defects in quantum k-CNOT gates. In this paper, we propose a new design-for-testability (DFT) technique for quantum reversible circuits that deploys bit-swapping using Fredkin gates. It is shown that in an (n x n) circuit implemented with k-CNOT gates, addition of only two extra inputs along with a few Fredkin gates yields easy testability in the circuit. The modified design admits a universal test set of size (n + k + 2) that detects all detectable missing gate faults in the original circuit, where k is the maximum number of controls used among all k-CNOT gates. The DFT overhead in terms of quantum cost is also much less compared to previous approaches.