A fast comparator with integrated small dual hysteresis and offset control

This paper presents the design of a fast comparator, where the dual hysteresis and the digital offset control are integrated in a source degenerated preamplifier stage. The selected architecture of the preamplifier stage, followed by a differential symmetrical OTA allowed easily to be achieved design requirements as 8mV hysteresis, 1σ input random offset of 0.58mV, range of ±35mV additional digital offset control with 5mV step, 30ns propagation delay, while the power dissipation is 90μW and the block area is 0.015mm² at 0.18μm CMOS technology. The source degenerating resistors in the preamplifier stage can be used to create dual or single, digitally programmed hysteretic comparators.