Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing

In this paper we present an efficient implementation of a serial/parallel two's complement multiplication scheme. The proposed implementation, provided in register transfer level VHDL code, can be synthesized to a variety of FPGA and ASIC technologies. Experimental results based on industry tools verify the efficiency of the multiplier in terms of speed and area. The proposed implementation can be used as a building block for intellectual property (IP) based development and rapid prototyping of VLSI digital signal processing systems.