3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface

In most of recent Networks-on-Chip (NoCs), a simple 2D mesh structure has been adopted. However, the increasing latency caused by the large number of hops has become a problem especially in a large chip multiprocessor with increasing number of cores. Although using low ASPL networks which can reduce the hop count is a hopeful solution, a number of long wires often limits the operational frequency. Hence, we propose 3D layout of three networks: Spidergon, Flattened Butterfly, and Dragonfly on a chip stack with wireless inductive coupling through chip interface (TCI). By making the use of TCI properties, including flexible stacking and chip pass-through data transfer, the maximum length of wires is much reduced. A large system which uses many chips can easily be implemented without degrading operational frequency.