Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells

The dominant errors for memories with multilevel cells are due to interference and low data retention which causes the threshold voltage to shift compared to its original value. Thus, the dominant error type is limited magnitude errors. Orthogonal Latin squares (OLS) codes have been used in SRAM for their low latency decoding. In this paper, OLS codes are extended to correct limited magnitude errors. The proposed codes aim at lowering the redundancy by considering only a few bits from each symbol to compute the parity bits. An efficient methodology for constructing the decoding logic necessary to correct limited magnitude errors is described. Also, new hybrid codes are proposed in this paper which combine the proposed limited magnitude OLS codes together with low redundancy error correcting codes to further reduce the number of check-bits with some additional decoding complexity.