Analysis of low power feed through logic with leakage control technique

In this article, novel leakage control techniques are adopted in Feed-Through Logic (FTL) for low power high-speed designs. The FTL design has a unique feature; the outputs are partially evaluated before its input data arrive and quick final evaluation is performed as soon as input signals reach. However, FTL designs suffer from high leakage and standby current in static and dynamic modes which increase the total power dissipation. To resolve this issue leakage control techniques such as Leakage Control Transistor (LCT) and Self-Biasing Transistor (SBT) are adopted. It acts as a smart switch by virtual power gating, which reduces the voltage swing, causing the significant reduction in static and dynamic power dissipation. In addition to that mixed-mode ripple carry adder approach has been introduced using projected and basic designs. Simulation has been executed through PTM 45 nm technology using the T-spice simulator. The parametric analyses are performed to examine the reliability of the circuit through the capacitive load, supply voltage variations and the immunity to thermal noise demonstrating the effectiveness of the proposed technique. Simulation results have demonstrated that the proposed approaches achieve low power-delay product.