Novel SRAM cells using dual-threshold independent-gate FinFETs

SRAMs play an important role for VLSI's performances. However, with the reduction of IC's feature size and power supply voltage, the reading and writing stability of the storage cells has been decreasing. This paper presents two novel seven transistor SRAM cells based on Dual-Threshold (DT) Independent-Gate (IG) FinFETs. The read and write operations are separated by adding a high threshold IG FinFET to improve stability. We utilize more design space of DT IG FinFETs to increase RSNM (Read Static Noise Margin) and WLWM (Word Line Write Margin), and reduce leakage power consumption. We optimize the DT IG FinFET devices by using titanium nitride (TiN_x) gate electrode with a tunable work function to obtain well performances. The TCAD simulations show that the I_on/I_off is improved significantly. HSPICE simulations indicate that the proposed SRAM cells obtain higher write margin and read static noise margin with lower leakage power consumption than the other implementations.