CMOS limitations and futuristic carbon allotropes

Based on ITRS predictions the existing CMOS Technology that has dominated IC industry for many decades is about to reach its physical scaling limit shortly [1]. Literature available online from various sources is sufficient to justify the limitations of CMOS technology below 22nm. These limitations include Symmetry problems, short channel effects, rise in quantum tunneling/ leakage current, increase in resistance etc. Devices like Silicon on Insulators (SOI), Fin-FETs, CNT-FETs, Resonant Tunneling Devices (RTDs) and Single Electron Devices (SEDs) have been researched over the time to identify the potential substitute of CMOS technology. Some Numerical simulations have been performed on these proposed devices partially to testify their capability to cater the future demands. These devices have been found much superior in electrical, mechanical, and thermal properties as compared to traditional CMOS technology that attracted researchers towards them. Use of such devices either on individual basis or in combined form can provide high performance features such as very high current carrying capacity, high gain, suitable for high frequency applications etc. The technology based on these devices after reaching a certain level of maturity will reduce their manufacturing costs and make them affordable. Before, microelectronic industry could exploit the potential of above mentioned devices; industry is facing difficulties of many types in their manufacturing like selection of a suitable fabrication/synthesizing technique offering minimum defects, Performing batch processing without any property variation, new set of scaling rules, different substrate materials etc. Many authors have reached an opinion after compiling the observations and investigations data from various authentic resources that CMOS technology can be further squeezed to dimensions lower than what ITRS has predicted earlier (i.e. 22nm). Microelectronic players like Intel and Samsung have already come up with a technology of ~10 nm and have already successfully used in their devices. It is expected that CMOS device shrinking will go at least up to 5nm in the future but, with lot of constraints and compromises. Literature based on CMOS limitations have been segmented in III parts in this paper. Sections I-II will move around CMOS scaling issues in brief; whereas, Section III explains the scope, applications and viability of futuristic devices in brief.