Design automation of testable finite state machines

The aim of the work is to develop a procedure for constructing models of testable control finite state machine (FSM), which are described using hardware description languages, and to estimate hardware costs for different methods of hardware redundancy introduction to the HDL model of FSMs. The task of computer-aided design of testable control FSM on the basis of the application of state machines' setting methods into a given state was solved in the work. In terms of hardware costs, the optimal way of settings organization in an arbitrary state of control FSM is expansion of the state table, which improves the controllability of the FSM's states and leads to the structure transformation of their HDL-models into easy-tested ones.