Timing modeling at RT-level by separation of design- and stress related aging impacts

The simulation of aging induced degradation mechanisms is a challenging task during the design of digital systems. Parametrical degradations can be handled most accurately at TCAD level, as the physical models like [1] and [2] can be implemented directly. On the other hand, timing failures caused by such degradations cannot be assessed exactly lower than Register Transfer Level (RTL), where the notion of clock delay and critical paths is introduced. Since System-Level designers have no influence on device level abstractions, this is the lowest level for them to perform optimization. However accurate and realistic timing estimation of different component designs at RTL under aging is problematic as entire components are either too large to be simulated by circuit level simulators like SPICE or the simulations become unacceptably slow. Thus a compact, accurate and efficient model for aging aware timing estimation at RTL is needed to support design technology co-optimization for digital circuits. This work evaluates a new RTL timing model concept with respect to accuracy and capability of separating design- and stress related impacts on aging, by applying different stress scenarios at RTL to a selection of ISCAS89 Benchmark circuits. The results indicate that the modeled timing estimations are sufficiently accurate, with average RMS of 1.13% for the deviation between circuit-level and the model. Results also demonstrate that the separation of design- and stress related aging impacts provided by the approach is adequate with average RMS of 2.06% respectively. This is a significant step towards a black box RTL timing model for aging assessment.