Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis

This paper presents the system architecture, modeling, and design constraints of a wireless chip-to-chip-communication transceiver as a low-power alternative to wireline links, such as PCI-Express. On top of the potential power savings, the wireless link provides lower latency times, better flexibility, lower complexity, and easier heat diffusion. The proposed transceiver uses impulse-radio ultra-wideband communication at 10 GHz. It supports a 2.5-Gb/s data rate with pulse position modulation over short distances (_~10 cm). The hardware complexity is reduced by using a modified non-coherent receiver with a rectifying RF front-end and a relative-compare analog baseband. The system performance is quantified and tradeoffs are explored with the main motivation of reducing power. A discussion of the modulation choice, the performance specifications of the receiver blocks and the clock generation principle is presented. We show that energy efficiency better than 6 pJ/bit could be reached with the proposed architecture.