Hardware efficient detection for massive MIMO uplink with parallel Gauss-Seidel method

In this paper, a novel, low-complexity, and hardware efficient signal detection algorithm and its corresponding VLSI architecture are proposed for massive multiple-input multiple-output (MIMO) systems. This method is based on the parallel Gauss-Seidel (PGS) iterative method, and achieves comparable detection performance as the linear minimum mean-square error (MMSE) detection. It successfully avoids explicit matrix inverse in uplink, and therefore effectively reduces the computational complexity of the massive MIMO detection problem. The proposed efficient architecture is able to reduce the processing latency per iteration. Furthermore, this architecture is scalable and can be easily reconfigured as the number of antennas increases. Reference implementation results on a Xilinx Virtex-7 FPGA for a 128 × 8 massive MIMO system demonstrate the advantages of the proposed PGS detector in terms of hardware efficiency over the state-of-the-art linear detectors.