An efficient scheduling and mapping using SMT solver and translating workflow of Matlab Simulink model to synchronous dataflow graph for multi-core DSP architectures

The design of emerging complex embedded real time systems adopts increasingly the concept of multi-core architectures. These systems present a complicated used applications, like the rapid evaluation of multimedia systems, signal processing, telecommunications, and automotive. However, key issues of system designing are tasks mapping and scheduling, memory architecture, and on-chip interconnects. While respecting the requirements of users quality in terms of execution time, latency, buffer size, energy, number of cores, etc. This paper shows a new technique of scheduling algorithm using the Satisfiability Modulo Theory (SMT) solving technologies which aim to minimize the latency with an optimal number of cores. SMT solvers are heavily influenced by the industrial needs and applications. The software part is modeled by the dataflow graphs in multi-core applications. In fact, Workflow is advised to be a successful method to program multi-core platforms. We propose a novel Workflow for an automatic transformation from a Simulink model to a synchronous dataflow (SDF) model. This automation presents efficient results in the latency metric which proves that 4-cores architecture is more efficient than 16-cores architecture on high communication delay.