FPGA-Based Collaborative Hardware Sorting Unit for Embedded Data Processing System

In recent years there has been a growing interest in Internet of Thing, Big Data and Mobile Internet. With the rapid growth of the amount of data in the embedded environment, using a traditional embedded processor is hard to satisfy the requirements of big data processing. Sorting is one of the fundamental operation in data processing and is also frequently used for search, filter, feature analysis and so on. It can contribute significantly to the overall execution time in a system. Existing techniques accelerate sorting using multiprocessor or GPUs, but it is impractical for embedded systems. In this paper, we propose a FPGA-based collaborative hardware sorting unit for embedded data processing. The waiting data is transferred from the embedded processor to our hardware sorting unit by the data bus, then a ordered sequence is given form hardware sorting unit and is returned to the embedded processor by data bus. The waiting data is processed in a pure hardware circuit, do not need anything software operation, so the calculating speed depends on the delay time of hardware circuit, which is faster than traditional iterative algorithm by software method. By the collaborative hardware unit, we can greatly reduce the processor load and improve the operation efficiency significantly. In addition, we can define the size of the data bit flexibly, we can also expend the scale of the unit by circuit topology.