A computationally efficient compact model for leakage in cross-point array

Cross-point architecture, while being appealing in consideration of high integration density, suffers from leakage through sneak paths across the array. The leakage current flowing through half-accessed and in some cases, unaccessed cells (and the corresponding leakage power) are important determinants of array performance. Proper estimation of these components is computationally challenging and often demands rigorous simulation efforts. This paper presents a computationally efficient compact model to assess the leakage in cross-point array employing threshold switch selectors. We provide closed form mathematical expressions that govern our model and explain the derivation methodologies. We analyze and verify the validity of the model by cross-checking with results from conventional rigorous array simulations. The model shows excellent matching (~99% accuracy) with rigorous simulations for different array sizes (16×16 through 256×256). The model has been tested with various ranges of selector OFF resistance (0.1 MΩ to 1 GΩ), interconnect resistance (1 mΩ/□ to 10 Ω/□) and access voltage (0.2V to 1V). The test results from the model show accurate response in comparison with those obtained from intensive array simulations.