Design and implementation of area efficient 2-parallel filter on FPGA using image system

Parallel FIR filter is widely used among various types of filter in Digital Signal Processing (DSP). This paper shows the design of area-efficient 2-parallel FIR filter using VHDL and its implementation on FPGA using image system. This paper gives the details basic blocks of area-efficient 2-parallel FIR digital filter. In this paper proposed 2-parallel digital FIR filter and area-efficient 2-parallel FIR filter are explained. Its simulation using Xilinx 14.2 are also discussed. It also presents the FPGA implementation of primary 2-parallel filter and area-efficient 2-parallel on Xilinx 14.2 Spartan 3E Starter Board XC3S500E chips and its results. Since adders are less weight in term of silicon area when compare with the multipliers, therefore multipliers are replaced by the adder to reduce area and delay of the parallel FIR filter. Xilinx ISE 14.2 is used for simulating the design of the filter.