Packet generators on field programmable gate array platform

With the growing speed of computer networks, we need to test our solutions, network conditions, and topologies using high-speed traffic generators. The main contribution of this paper is 1) the theoretical proposal of a pseudo-random number generator (PRNG) algorithm that is usable for hardware-accelerated IP traffic generators and 2) the practical proposal of a novel design and implementation of an FPGA-based traffic generator that provides the high-speed generation of IP traffic for testing purposed, in particular for the Denial-of-Service (DoS) security testing. We present a solution for network cards based on FPGA and the NetCOPE development platform, in particular the NFB-40G2 cards. Using this platform, we explain the process of creating an IP packet and propose the VHDL architecture of the packet generator.