N-D SVPWM With DC Voltage Balancing and Vector Smooth Transition Algorithm for a Cascaded Multilevel Converter

Direct current voltages unbalance of respective power cells is an inherent and critical problem in a cascaded multilevel converter, which is widely used in the solid-state transformer. In this paper, an n -dimension space vector pulse width modulation is presented to address this issue in a three-level H-bridge-based cascaded multilevel converter. This algorithm utilizes the redundant switching pairs of the inner cell and the redundant vectors of mutual cells to balance capacitors' and cells' voltages. Meanwhile, a smooth vector transition strategy is included in this algorithm to avoid the level-skip phenomenon. The calculation processes are analyzed in one-cell, two-cells, and three-cells modes, respectively. It is simple, calculable, and flexible to extend in n-cells mode. Finally, the voltage balancing capacity of the inner cell and mutual cells with smooth level transition are verified by simulations and experiments not only at startup but also with unbalanced loads.