Pre-layout decap allocation for power supply noise suppression and performance analysis of 512-point FFT core

This paper deals with the estimation of decoupling capacitance (decap) based on their power supply noise suppression and proper allocation of decap at the pre-layout level. By early prediction and allocation of decap at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing noise, power and delay effects for the circuit. The novelty of our work lies in exhaustive estimation of power supply noise, followed by an algorithmic estimation and appropriate allocation of decap with an effort to keep noise, delay and power performance to its best. We choose 512-point FFT processor for our test circuit. To the best of our knowledge Power Distribution Network (PDN) analysis for execution time and noise suppression on FFT application cores is not available in related research works. By using our approach, power supply noise has been suppressed by 37.7%, delay and power consumption increases by 1.12% and 2.03% respectively at the pre-layout stage. This early predictions helps to create more accurate design at the layout stage and hence this work can serve as benchmark for PDN analysis.