Radix-4 adder design with refined carry

Adder is a critical component in arithmetic and logic units (ALUs). Minimizing the power consumption and delay of adder is an important issue. In this paper, we proposed a high performance multiplexer-based radix-4 adder with refined carry to reduce the propagation delay. To achieve high performance, the proposed radix-4 adder adopts multiplexers which are controlled by the carry signal of previous stage to avoid the long carry chain. The drivability of all outputs is strong because all outputs are full voltage swing. The proposed design was simulated by using the TSMC CMOS 45 nm technology. For 32-bit adders, compared with the previous radix-4 adder and 2-bit carry select adder, our design can reduce 16% and 19% delay, respectively; our design also achieves 13% and 66% EDP reduction, respectively.