Design of radix 2 butterfly structure using vedic multiplier and CLA on xilinx

FFT (Fast Fourier Transform) and IIFT (Inverse Fast Fourier Transform) structure plays very critical role in designing of digital signal processing. These structures are most commonly implemented on Application Specific Integrated Circuit (ASIC) for high performance. Butterfly structure is the basic unit of FFT and IIFT implementation. Each butterfly unit consists of complex multiplication and addition. Efficient implementation of these component plays very critical role in design of butterfly structure. Vedic Multipliers is one of the fastest and low power multiplier over corresponding other multiplier such as array and booth multipliers. This paper describes the design of butterfly structure using Vedic multiplier and CLA (Carry look Ahead adder) on Xilinx ISE Design suite 14.7 (FAMILY SPATAN 3E AND DEVICE XC3S1200E) platform and compared the same with other technique such as with RADIX-4 booth multiplier, RCA (Ripple Carry Adder).