vfTLP characteristics of ESD diodes in bulk si gate-all-around vertically stacked horizontal nanowire technology

For sub-7nm bulk Si CMOS, a gate-all-around (GAA) nanowire (NW) device is a promising candidate. The new device architecture will have impact on the transient performance of an ESD protection diode. vfTLP measurement results and TCAD simulations prove that the performance in bulk GAA NW based diodes is maintained in comparison to bulk FinFET diodes.