A multi-megabit memory compiler: tomorrow's IP [integrated processor]

Millions of bits of memory are sometimes required in today's system-on-a-chip designs. The scarcity of large ASIC memories forces designers to build their multi-megabit memories from smaller ones, with a concoction of design and analysis tools. This method can lead to many problems. We have developed a multi-megabit memory compiler that carries the full burden of the design assembly, verification and characterization for the ASIC designers. It saves valuable time and alleviates the risk for ASIC designers. In this paper, we describe the creation of the multi-megabit memory compiler with a set of commercially available EDA (electronic design automation) tools.