A tightly coupled hybrid SIMD/SISD system

This paper presents a proposed processing system based on a single instruction stream, multiple data stream (SIMD) architecture that is tightly coupled with a host processor. The system is designed with the objective of maintaining a low-latency SIMD instruction issue by reducing the overhead introduced by the path between the host processor and SIMD machine. The target applications are those that need a mixture of single instruction, single data (SISD) and SIMD instructions.