Hardware and software implementation of a stereoscopic image compression technique for internet connected devices

Image acquisition, analysis, compression and transmission have become mandatory tasks in embedded systems and internet connected devices. Compression and size reduction techniques increases the number of images stored on a memory space and reduces bandwidth consumption while increasing transmission speed on a communication channel and internet connected nodes. Images can be compressed and decompressed using different methods and algorithms. With the high demand on quality and the vast increase in size, dedicated processors with reconfigurable hardware such as FPGAs are mainly targeted to implementing faster processing circuits and algorithms for deployable devices. This paper presents a hardware and software implementation for a stereoscopic image compression algorithm using least significant bit watermarking suitable for embedded processors and Internet connected devices minimizing bandwidth consumption where continuous communication is needed.