Insulation design and evaluation via partial discharge (PD) test for power electronics application

Insulation design is important for medium voltage level, high power density power electronic equipment. This is especially true in order to achieve a high reliability and long lifetime, in conjunction with a reasonable insulation size and weight that is important for electric ship applications. Most of the weak points inside the solid insulation are located in the void or defect inside insulation, especially those near the field crowding area. An example of this is a self-made laminated bus. This paper will show how to model the actual structure and perform the electric field analysis, even with a single void. In order to reduce the stress for the insulation, several useful methods to decrease electric field crowding will be discussed. All these methods will be verified by FEA simulation. Then, a non-destructive partial discharge (PD) method to evaluate insulation will be introduced. The self-made laminated bus PD behavior under the line frequency sinusoidal and DC excitation will be captured. Later, a simple PCB coupon will be tested and its PD behavior under 60Hz sinusoidal and 60Hz unipolar square wave will be shown separately. These will somehow, demonstrate the difference between the insulation aging mechanism, especially under PWM-like excitation. However, deep understanding in how to evaluate and improve the insulation, especially as it applies to power electronics applications, needs to be explored in future work.