Design of process variation tolerant domino logic keeper architecture

Background/Objectives: Domino logic designs are widely used owing to its high speed and less area. However, the on chip variation of the design becomes more severe on scaling down the technology nodes. Methods/Statistical analysis: This paper details the design of variation tolerant domino logic with novel keeper architecture which comprises of a stacked grounded keeper with a body-bias generator. Furthermore, this paper elaborates the process variation tolerance techniques and compares the proposed keeper style with the existing styles. The design and analysis are carried out on wide fan-in domino logic circuits using Cadence^® Spectre and Monte Carlo simulations in ADE-XL environment Findings: The results demonstrate that the novel variation tolerant keeper has an advantage of less delay compared to the conventional keeper. Additionally, it offers lesser delay variability of 7.24% and 9.18% and power variability of 14.01% and 0.15% using 180nm and 45nm technology libraries. Improvements/Applications: The proposed architecture enables the domino logic circuits to be used in applications that require robust and fast processing.