Verification of fault tolerant techniques in finite state machines using simulation based fault injection targeted at FPGAs for SEU mitigation

Field Programmable Gate Arrays (FPGA) are susceptible to soft errors due to the shrinkage of feature size and reduction in core voltage which reduces the critical charge required to change the state of a circuit element. To improve the reliability and availability of the FPGA based designs used in Nuclear Power Plants special care has to be taken against these emerging risks. In this paper, the effects of radiation on Finite State Machines (FSM) is reviewed and resource utilization and performance penalty are analyzed by using the fault tolerant techniques like Triple Modular Redundancy (TMR), Hamming-3 encoding and safe FSM synthesis. A novel scripting based fault injection technique is proposed for verifying the fault tolerant techniques at netlist level. The PREP3 state machine is used as a benchmark circuit in this paper. This work predominantly focuses on the practical use of fault tolerant techniques such as TMR, Error Detection and Correction by using Hamming-3 encoding for state register and Safe FSM implementation in live designs targeted at Nuclear Power Plants in India. The major objective of this work is to review the various field proven fault tolerant techniques targeted at FPGAs and develop a simple scalable methodology for verification of the same.