Study of error repeatability and recovery in 40nm TaOx ReRAM

The repeatability of set/reset errors has been investigated in 40nm TaOx based ReRAM cells. Errors of the Low Resistance State (LRS) in specific cells are observed repeatedly, and such cells are recovered by DC read operation. When error cells are recovered, the LRS cell current of the recovered cells shows a sudden jump up to large cell current in certain set cycles. Then, the High Resistance State (HRS) current is also recovered from almost no current to normal HRS current. The phenomena of repeating error can be explained as lack of oxygen vacancy in specific cells which have a wide conductive filament. Moreover, the error repeated cells have larger LRS cell current than the normal LRS cell current after recovery. Thus, the potential error repeated cells can be detected by cell current check sequences, which detect to repeat the larger LRS cell current. The failure rate can be reduced by replacing the error repeated cells with redundant cells.