A reconfigurable digital filter chip for image processing

The scope of this paper is to present a Programmable Digital Filter (PDF) design. This architecture can be programmed to implement any eight order Infinite Impulse Response (IIR) or Finite Impulse Response (FIR) filters. The coefficient, input and output data word lengths are coded on 16 bit, internal results are on 32 bit. A first low cost VLSI implementation of this architecture was validated and tested successfully in a 0.7 /spl mu/m CMOS technology, with an area of 27 mm/sup 2/ and a maximum clock frequency of 40 MHz. The migration in a 0.25 /spl mu/m CMOS process allows us to reach a 150 MHz clock frequency with an area of 5 mm/sup 2/. A specific board has been developed for fast prototyping of real time image processing applications.