Design of dynamic circuits with enhanced noise tolerance

In this paper, we present a design technique that increases the noise tolerance of dynamic circuits. We present a low-noise circuit which has very low leakage and variable input noise margin. This circuit can be used in the design of noise-tolerant dynamic wide-OR gates which are otherwise extremely vulnerable to noise at the inputs and charge leakage from the dynamic evaluation node. High speed decoders and comparators used in a cache can be realized using dynamic wide-OR gates. We present simulation results to demonstrate the effectiveness of the proposed design technique compared to other techniques. We also present the application of the low-noise circuit to enhance the noise immunity of dynamic SOI gates against parasitic bipolar leakage.