Performance enhancement through optimal n-tier multilevel interconnect architectures

A stochastic wire-length distribution is used to develop an optimal n-tier multilevel interconnect architecture for a 0.1 /spl mu/m ASIC macrocell. The results of the n-tier design when compared to the 2-tier design show a 30% reduction of metal levels, three fold reduction in macrocell area or three fold increase in clock frequency.