Design and analysis of LDMOS_SCR with narrow windows

In this paper, an improved LDPMOS_SCR without a LDPMOS structure (NonLDPMOS_SCR) is discussed, which is realized in 0.5-μm 5V/18V/24V CDMOS process. The theoretical analysis and transmission line pulse (TLP) testing system are used to predict and characterize the proposed ESD protection devices. According to the measurement results, compared with the normal LDPMOS_SCR, NonLDPMOS_SCR elevates the second breakdown current (It2) from 3.87A to 4.64A and decreases the trigger voltage (Vh) from 33V to 21.4V without expanding device area. Furthermore, the influence of the size of D2 and D3 (as shown in Fig.1(c)) on holding voltage is discussed. The TLP results confirm that by adding the width of D2, the holding voltage is increased from 11.7V to 14.79V. And by adding the width of D3, the holding voltage is increased from 11.7V to 15.9V. It is proved that increasing the width of D3 in the proposed device is more effective in increasing the holding voltage.