Novel electrostatic discharge (ESD) clamp circuit with low leakage current

A novel electrostatic discharge (ESD) clamp circuit for power-rail ESD protection, consisting of the stacked transistors and biased RC network, is proposed in a 90 nm CMOS process. The biased RC network possesses a small footprint and the detection circuit has a pretty low leakage current of up to 12 nA under normal operation. The proposed ESD clamp circuit has a long hold-on time of 800 ns under the ESD event and a quick turn-off mechanism for false triggering. SPICE simulation is carried out to evaluate the ESD clamp, and comparing with the conventional designs, the simulation results suggest that the proposed circuit has a lower power consumption and smaller footprint while achieving better performance.