Timing error performance analysis for low power DSP filters

Circuit-level timing error detection and correction technique, which aims to increase energy-efficiency of digital signal processing data paths. It is important to develop a high-performance FIR filter to meet the requirements of real-time, low power, low cost and small area in different applications. Razor Flip-flop based dynamic voltage scaling error detection technique which is used to eliminate the supply voltage margin. Razor flip flop is used to detect the timing errors on Critical Path. The FIR filter based on Razor for every bit and the error bit is generated and one can overcome the error with the help of filter. The proposed Filter can be used for any DSP application. The Razor based FIR filter is synthesized and simulated using VHDL. Finally the Razor based approach is applied to Multiplier and performance is analyzed. Designed filter is verified with the 8 Bit multiplication and the output is achieved without error because of the Razor used in each bit of the filter.